Russian Federation
Voronezh, Russian Federation
Russian Federation
Russian Federation
Russian Federation
This article discusses the development of effective methods and tools for assessing the fault tolerance of logical circuits, the mechanism of logical masking, the development of the route of re-synthesis of combinational circuits, methods for increasing fault tolerance. A method of iterative circuit modification is proposed, due to an increase in the level of logical masking of the circuit.
heavy charged particles, microelectronics, fault tolerance of logic circuits, logi-cal masking, methods for assessing fault tolerance
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