Russian Federation
The article discusses the application of the UVM-MS (Universal Verification Methodology for Mixed-Signal) methodology for automating the verification of analog-digital paths in modern Systems-on-Chip (SoCs). The relevance of transitioning from outdated methods to a standardized approach is justified against the backdrop of increasing complexity in heterogeneous chips. Using the verification of a 12-bit Successive Approximation Register ADC (SAR ADC) with an SPI interface as an example, the architecture of the testbench is described in detail, including key components of the standard: the MS Bridge, the reference model, and the scoreboard. The results of applying the methodology are presented, demonstrating a significant increase in functional coverage, a reduction in debug time, and the enablement of reusable verification components. The conclusion highlights the strategic importance of adopting UVM-MS to improve quality and reduce risks in the development of mixed-signal SoCs.
UVM-MS, mixed-signal verification, System-on-Chip (SoC), ADC, automation, functional coverage, SystemVerilog, reference model, reuse, MS Bridge
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